Patent Catalogue


Header field including a plurality of address regions having recorded therein address information, address synchronous information, and clock synchronous information.

  • Address information has been modulated using a run length limit code of a minimum inversion interval of Tmin bits and a maximum inversion interval of Tmax bits.
  • Clock synchronous information is a sequential pattern of alternate repetition of a first and a second pattern having a length of d bits, d being a natural number satisfying Tmin < d < Tmax.
  • Address synchronous information includes two patterns having a length of (Tmax + 3) bits or more, and being reversed each other.


  • DVD-RAM Part1 Figure (a)/PH5-6 5.2.2/PH5-8, 5.2.3/PH5-8, 5.2.4/PH5-9,5.3/PH5-27

[Offering Patent]

  • USP 6,208,603

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